verilog39 DecodeAddress module DecodeAddress #(parameter ADDR_WIDTH = 1)( output [$pow(2,ADDR_WIDTH) - 1:0] Decoded, input [1:0] DigitSupply, input Enable, input [ADDR_WIDTH-1:0] ToDecode); wire [$pow(2,ADDR_WIDTH)-1:0] Decoded; tri [1:0] DigitSupply; tri Enable; tri [ADDR_WIDTH-1:0] ToDecode; tri [$pow(2, ADDR_WIDTH+1)-1:1] Buffer; assign Buffer[1] = Enable; genvar IndexToDecode; .. 2024. 5. 19. DecodeAddress1Bit module DecodeAddress1Bit( output [1:0] Decoded, input [1:0] DigitSupply, input Enable, input ToDecode ); wire [1:0] Decoded; tri [1:0] DigitSupply; tri Enable; tri ToDecode; tri ORed; tri ANDed; tri Compared; or_nB_to_A MakeORed(ORed, DigitSupply, DigitSupply[0], DigitSupply[0]); and_nB_to_A MakeANDed(ANDed, DigitSupply, ORed, DigitSupply[0]); .. 2024. 5. 9. NegEdge module NegEdge( output Edge, input [1:0] DigitSupply, input Clock ); reg Edge; tri Clock; tri nClock; _not InvertClock(nClock, DigitSupply, Clock); PosEdge MakeResult(Edge, DigitSupply, nClock); endmodule 2024. 5. 9. PosEdge module PosEdge( output Edge, input [1:0] DigitSupply, input Clock ); wire Edge; tri Clock; tri LatchedClock; D_Latch MakeLatch(LatchedClock, DigitSupply[1], Clock, DigitSupply[1]); and_nB_to_A MakeEdge(Edge, DigitSupply, Clock, LatchedClock); endmodule 2024. 5. 9. 이전 1 2 3 4 5 6 7 8 ··· 10 다음