verilog39 DifferentialQBit `include "DigitSupply.vh" module DifferentialQBit( inout QBitN, inout QBitS ); tri QBitN; tri QBitS; tri NorthToSouth1; tri SouthToNorth1; trireg NorthToSouth2; trireg SouthToNorth2; _nmos ChargeNorth(NorthToSouth1, QBitN, Vdd); _nmos ChargeSouth(SouthToNorth1, QBitS, Vdd); assign NorthToSouth2=NorthToSouth1; assign SouthToNorth2=SouthToNor.. 2025. 6. 8. GitHub Verilog/Verilog at main · dbdan114/Verilog 2025. 2. 26. Advanced DDR_SPS_DRAM `include "DigitSupply.vh" module DDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh, input nClock); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; .. 2025. 1. 12. Advanced SDR_SPS_DRAM `include "DigitSupply.vh" module SDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; tri Write; t.. 2025. 1. 11. 이전 1 2 3 4 5 ··· 10 다음