verilog39 DDR_SRAM `include "DigitSupply.vh" module DDR_SRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input nClock); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; tri Write; tri nC.. 2024. 12. 31. SDR_SRAM `include "DigitSupply.vh" module SDR_SRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; tri Write; tri [1:0] ChargedPu.. 2024. 12. 31. DDR_SPS_DRAM `include "DigitSupply.vh" module DDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh, input nClock); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; .. 2024. 7. 24. SDR_SPS_DRAM `include "DigitSupply.vh" module SDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; tri Write; t.. 2024. 7. 24. 이전 1 2 3 4 5 6 ··· 10 다음