verilog39 _pmos module _pmos( output reg outputData, input tri inputData, input tri Control ); //reg outputData; //tri inputData; //tri Control; always @(*) begin if(Control == 1'b1) outputData=1'bz; else if(Control == 1'b0) outputData=inputData; else outputData= 1'bx; end endmodule 2024. 7. 14. _nmos module _nmos( output reg outputData, input tri inputData, input tri Control ); //reg outputData; //tri inputData; //tri Control; always @(*) begin if(Control == 1'b1) outputData=inputData; else if(Control ==1'b0) outputData=1'bz; else outputData= 1'bx; end endmodule 2024. 7. 11. advanced CellOfDRAM `include "DigitSupply.vh"module CellOfDRAM( output outputData, input ReadEdge, input inputData, input WriteEdge, input RefreshEdge ); tri outputData; tri ReadEdge; tri inputData; tri WriteEdge; tri RefreshEdge; tri ChangedWriteEdge0; tri ChangedWriteEdge1; tri ChangedReadEdge0; tri ChangedReadEdge1; tri PreDataToWrite; tri DataToWri.. 2024. 6. 12. advanced D_Latch `include "DigitSupply.vh"module D_Latch( output outputData, input ReadEdge, input inputData, input WriteEdge ); tri outputData; tri ReadEdge; tri inputData; tri WriteEdge; tri ChangedWriteEdge0; tri ChangedWriteEdge1; tri ChangedReadEdge0; tri ChangedReadEdge1; tri DataWest; tri DataNorth; tri DataSouth; tri DataEast; _buf ToWest(.. 2024. 6. 12. 이전 1 2 3 4 5 6 7 ··· 10 다음