verilog39 IC_Example `include "DigitSupply.vh" module IC_Example ( /* To Write Your Signal*/ /* To Write Your Signal*/ ); tri QBitToRead; tri QBitToWrite; tri WrtingToQBit; tri AddressQBit; tri QRAM_DDRClockP; tri QRAM_DDRClockN; assign QBitToWrite = rVss; assign WrtingToQBit = rVdd; QRAM_inSDRAM MakeQRAM(QBitToRead, Vdd, QBitToWrite, WrtingToQBit, QRAM_DDRClockP, QR.. 2025. 6. 11. QRAM_inSDRAM `include "DigitSupply.vh" module QRAM_inSDRAM ( output outputQBit, input Read, input inputQBit, input Write, input AddressQBit, input DDRClockP, input DDRClockN ); tri PosEdgeClockForAddressQbit; tri NegEdgeClockForAddressQbit; tri DualEdgeClockForAddressQbit; tri PosEdgeClockForDataQBit; tri NegEdgeClockForDataQBit; tri DualEdgeClockForDataQBi.. 2025. 6. 8. CellOfQRAM `include "DigitSupply.vh" module CellOfQRAM( output outputData, input ReadEdge, input inputData, input WriteEdge ); tri outputData; tri ReadEdge; tri inputData; tri WriteEdge; tri West; tri North; tri South; tri East; _nmos Write(West, inputData, WriteEdge); assign North=West; assign South=West; DifferentialQBit UseQBit(No.. 2025. 6. 8. OscilateFromXtalDDR `include "DigitSupply.vh" module OscilateFromXtalDDR( input Xtal1, input Xtal2, output ClockP, output ClockN ); tri Xtal1; tri Xtal2; tri North; tri South; assign North=Xtal1; assign South=Xtal2; reg ClockP; reg ClockN; DifferentialQBit Rectify(North,South); _buf(ClockP,PullDigit,North); _buf(ClockN,PullDigit,South); endmodule 2025. 6. 8. 이전 1 2 3 4 ··· 10 다음