DRAM17 Advanced DDR_SPS_DRAM `include "DigitSupply.vh" module DDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh, input nClock); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; .. 2025. 1. 12. Advanced SDR_SPS_DRAM `include "DigitSupply.vh" module SDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; tri Write; t.. 2025. 1. 11. DDR_SPS_DRAM `include "DigitSupply.vh" module DDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh, input nClock); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; .. 2024. 7. 24. SDR_SPS_DRAM `include "DigitSupply.vh" module SDR_SPS_DRAM #(parameter ADDR_WIDTH = 1parameter DATA_WIDTH = 1)( inout [DATA_WIDTH - 1 : 0] inoutData, input [ADDR_WIDTH - 1 : 0] Address, input Clock, input Enable, input Read, input Write, input Refresh); reg [DATA_WIDTH - 1 : 0] inoutData; tri [ADDR_WIDTH - 1 : 0] Address; tri Clock; tri Enable; tri Read; tri Write; t.. 2024. 7. 24. 이전 1 2 3 4 5 다음