verilog39 CellOfDRAM //`include "./DigitSupply.v" /*supply0 Vss; supply1 Vdd; tri [1:0] SupplyDigit= {Vdd,Vss}; tri0 rVss; tri1 rVdd; tri [1:0] PullDigit= {rVdd, rVss};*/ `include "DigitSupply.vh"module CellOfDRAM( output outputData, input Read, input inputData, input WriteEdge, input RefreshEdge ); tri outputData; tri Read; tri inputData; tri WriteEdge; tri Refr.. 2023. 11. 17. D_Latch `include "DigitSupply.vh"module D_Latch( output outputData, input ReadEdge, input inputData, input WriteEdge ); tri outputData; tri ReadEdge; tri inputData; tri WriteEdge; tri DataWest; tri DataNorth; tri DataSouth; tri DataEast; _buf ToWest(DataWest,SupplyDigit,inputData); _nmos WestToNorth(DataNorth,DataWest,WriteEdge);//Sup.. 2023. 11. 16. "DigitSupply.vh" SupplyDigit PullDigit supply0 Vss; supply1 Vdd; tri [1:0] SupplyDigit= {Vdd,Vss}; tri0 rVss; tri1 rVdd; tri [1:0] PullDigit= {rVdd, rVss}; 2023. 11. 12. or_nB_to_A module or_nB_to_A( output outputData, input [1:0] DigitSupply, input A, input nB ); wire outputData; tri [1:0] DigitSupply; tri A; tri nB; _pmos For0(outputData,DigitSupply[1],nB); _nmos For1(outputData,A,nB); endmodule 2023. 11. 11. 이전 1 ··· 5 6 7 8 9 10 다음