verilog39 or_B_to_A module or_B_to_A( output outputData, input [1:0] DigitSupply, input A, input B ); wire outputData; tri [1:0] DigitSupply; tri A; tri B; _pmos For0(outputData,A,B); _nmos For1(outputData,DigitSupply[1],B); endmodule 2023. 11. 11. and_nB_to_A module and_nB_to_A( output outputData, input [1:0] DigitSupply, input A, input nB ); wire outputData; tri [1:0] DigitSupply; tri A; tri nB; _pmos For0(outputData,A, nB); _nmos For1(outputData,DigitSupply[0], nB); endmodule 2023. 11. 10. and_B_to_A module and_B_to_A( output outputData, input [1:0] DigitSupply, input A, input B ); wire outputData; tri [1:0] DigitSupply; tri A; tri B; _pmos For0(outputData,DigitSupply[0], B); _nmos For1(outputData,A, B); endmodule 2023. 11. 10. _buf module _buf( output outputData, input [1:0] DigitSupply, input inputData ); wire outputData; tri [1:0] DigitSupply; tri inputData; _pmos For0(outputData,DigitSupply[0],inputData); _nmos For1(outputData,DigitSupply[1],inputData); endmodule 2023. 11. 10. 이전 1 ··· 6 7 8 9 10 다음