CellOfDRAM

//`include "./DigitSupply.v"
/*supply0 Vss;
supply1 Vdd;
tri [1:0] SupplyDigit= {Vdd,Vss};

tri0 rVss;
tri1 rVdd;
tri [1:0] PullDigit= {rVdd, rVss};*/

`include "DigitSupply.vh"

module CellOfDRAM(
    output outputData,
    input Read,
    input inputData,
    input WriteEdge,
    
    input RefreshEdge
    
    );
    tri outputData;
    tri Read;
    tri inputData;
    tri WriteEdge;
    tri RefreshEdge;
    
    tri PreDataToWrite;
    tri DataToWrite;
    //tri ProDataToWrite;
    trireg LatchOfDRAM;
    tri DataToRead;
    tri DataToRefresh;
    
    
    _buf InputToSupplyStrength(PreDataToWrite,SupplyDigit,inputData);
    _nmos InsertWriting(DataToWrite,PreDataToWrite,WriteEdge);
    _nmos InsertRefreshing(DataToWrite,DataToRefresh,RefreshEdge);
    //_buf ToSupplyStrength(ProDataToWrite,SupplyDigit,DataToWrite);
    _nmos SendToTriReg(LatchOfDRAM,DataToWrite,1'b1);//_nmos SendToTriReg(LatchOfDRAM,ProDataToWrite,1'b1);//assign LatchOfDRAM=ProDataToWrite;//_nmos SendToTriReg(LatchOfDRAM,ProDataToWrite,SupplyDigit[1]);
    _buf ToRefresh(DataToRefresh,PullDigit,LatchOfDRAM);
    _buf ToRead(DataToRead,2'b10,LatchOfDRAM);
    _nmos InsertReading(outputData, DataToRead ,Read);//_nmos InsertReading(outputData,DataToRead,Read);
endmodule