module _buf(
output outputData,
input [1:0] DigitSupply,
input inputData
);
wire outputData;
tri [1:0] DigitSupply;
tri inputData;
_pmos For0(outputData,DigitSupply[0],inputData);
_nmos For1(outputData,DigitSupply[1],inputData);
endmodule
'verilog' 카테고리의 다른 글
| and_nB_to_A (0) | 2023.11.10 |
|---|---|
| and_B_to_A (0) | 2023.11.10 |
| _not (0) | 2023.11.10 |
| _pmos (0) | 2023.11.10 |
| _nmos (0) | 2023.11.10 |